An 8 Bit (Cascaded 4 Bits) Dual Slope ADC

Abstract

The purpose of this thesis was to create and understand the use of a dual slope ADC using Two (2) 4 Bits cascaded counters.

During the process of this thesis, both a simulation and actual laboratory works were done to compare and verify the operations as compared to the theory being investigated. The making of this Dual Slope ADC was first done by creating the various parts of operation in pieces to check they function before finally putting them all together. This design was first done with the help of MULTISM simulation tool where all the design was made and the use of Ultiboard to print out the PCB layout with the 3D view.

After the simulation was done to check for errors and it efficiency, the design was made in the Laboratory and various measurements are taken. With the help of the data collected in the Lab, one was able to determine the operation of the Dual slope ADC.

The conclusion of the study showed the efficiency of the Dual slope ADC as compared to other ADCs, most especially the Single slope ADC.