FPGA-based BLDC motor controller

Abstract

Field-Programmable Gate Arrays are a common choice for integrated circuit design that requires fast signal handling and frequent modification during the development process. An FPGA was used in this project for the exact reason of it being scalable and continuously improvable. The creation of this type of a device requires clear and concise workflow and -planning.

The objective of this thesis was to create an FPGA-based brushless direct-current(BLDC) motor controller. The work for this thesis was implemented in two parts: hardware- and code creation. Both parts were handled with the same workflow in parallel. The workflow happened in five steps: research, requirements definition , implementation, testing, and analysis.

The hardware description language used for the FPGA was VHSIC hardware description language(VHDL). The architecture was built by the author of this thesis based on research of previous implementations and the requirements defined for the controller. The hardware was based on the capabilities of the FPGA development board and the requirements of the BLDC motor used for testing. With this method, a basic BLDC motor controller was created and tested.

As a result, this thesis serves as an easy-to-understand document introducing the technologies required for a BLDC motor controller and describing the process of developing said controller. The final VHDL code was added, which can be used to implement an FPGA motor controller, and schematics which can be used to assemble the hardware for this controller.