Strategic efficiency management assessing and improving the effectiveness of SoC Architecture teams in semiconductor industry

Abstract

This thesis investigates the efficiency management of System-on-Chip (SoC) Architecture teams, with a focus on improving existing metrics to better capture the team’s multifaceted performance and operational complexity. The primary objective is to address gaps in current performance indicators and propose refined Key Performance Indicators (KPIs) that more accurately reflect the team’s productivity, quality management, and strategic alignment.

The research employs a mixed-methods approach, combining qualitative semi-structured interviews with 28 key stakeholders and quantitative structured surveys to gather comprehensive data on the current efficiency measurement practices within the architecture team. Key findings indicate that while current KPIs such as Harvested Effort vs. Total Capacity and Average Fault Correction Time provide essential insights into productivity and responsiveness, they fail to fully capture critical factors such as role clarity, collaboration dynamics, and the quality of external inputs.

Significant inefficiencies were identified in areas including communication, stakeholder alignment, and resource management, suggesting the need for more holistic performance metrics. The thesis recommends the adoption of additional KPIs, such as Review Cycle Efficiency and Stakeholder Alignment Index, to enhance the measurement of both process and output efficiency, as well as cross-functional collaboration.

Ultimately, this thesis contributes to improving the efficiency of SoC architecture teams by offering actionable recommendations that address both qualitative and quantitative dimensions of team performance, enabling them to better meet project goals, improve innovation, and maintain alignment with organizational strategies in the fast-paced semiconductor industry.