Tunable Microwave Phase Locked Oscillator : Phase Locked Loop Implementation

Abstract

The demand for high data rates and low power consumption has had a major impact on the design of RF frequency synthesis systems. The need for highly stable oscillators is one of the main driving force in most communication systems that utilise the super heterodyne architecture. Not only the communication systems, but a variety of measurement equip-ment require a low noise local oscillator such the spectrum analyser.

The goal of this thesis work was to design and analyse frequency synthesis in the micro-wave range for laboratory use. The design utilises the Analog Devices ADF4155 Phase Locked Loop synthesizer integrated circuit. The chip incorporates the control circuitry re-quired to implement a phase locked oscillator.

The Phase Locked Oscillator system compromises the ADF4155 PLL, Zcomm V940ME03 Voltage Controlled Oscillator and a fourth order Loop Filter. The thesis concentrates mainly on the design and analysis of the loop filter and the characterisation of the phase noise of the generated signal.

Finally, an L-Band signal of 1.45 GHz is generated and phase noise measurement is done. The measured value of the phase noise is compared with the simulated value. Further work may involve doing measurements on frequency settling time and phase jitter of the generated signal.