Prescaler for a Phase Locked Oscillator
Gautam, Bigyan (2019)
2019
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:amk-2019112522355
https://urn.fi/URN:NBN:fi:amk-2019112522355
Tiivistelmä
The main goal of this project was to design a test circuit for a prescaler to be used in a phase locked oscillator. Phase locked oscillator operates on the principle of PLL. Phase locked loop (PLL) refers to a control system which generates an output signal with respect to the input signal phase and feedback. The circuit is constantly adjusted so that the frequency of the output signal is locked to that of input. The PLL has become an integral part of modern day communication systems and is widely implemented in radio communication, mobile phones and GPS systems. One of the main components of a PLL oscillator is the prescaler circuit.
To implement the prescaler circuit a PCB was designed using KiCad, an open source circuit design software and printed. A 1.1 GHz prescaler was used for low power frequency division.
The main function of a prescaler is to perform frequency division on the input signal. The prescaler designed for this thesis study can perform frequency division by a number of factors, i.e. 10, 20, 40 and 80. This division factor can be controlled by high or low signal in three pins placed on the PCB. Upon completion, a PCB that could perform the aforementioned divisions was created and then tested at different frequencies under the operating frequency range of the prescaler, to verify that the desired results would be achieved.
Different measurements were performed to determine the ideal/best operating conditions for the PLL oscillator where the designed prescaler circuit would be implemented. A PLL oscillator has a wide range of applications in terms of signal synchronization and it can be implemented in numerous modern communication and radio devices with output frequencies that range from fraction of hertz to gigahertz. With further improvements in design and assembly process, a prescaler which could yield better results circuit can be obtained.
To implement the prescaler circuit a PCB was designed using KiCad, an open source circuit design software and printed. A 1.1 GHz prescaler was used for low power frequency division.
The main function of a prescaler is to perform frequency division on the input signal. The prescaler designed for this thesis study can perform frequency division by a number of factors, i.e. 10, 20, 40 and 80. This division factor can be controlled by high or low signal in three pins placed on the PCB. Upon completion, a PCB that could perform the aforementioned divisions was created and then tested at different frequencies under the operating frequency range of the prescaler, to verify that the desired results would be achieved.
Different measurements were performed to determine the ideal/best operating conditions for the PLL oscillator where the designed prescaler circuit would be implemented. A PLL oscillator has a wide range of applications in terms of signal synchronization and it can be implemented in numerous modern communication and radio devices with output frequencies that range from fraction of hertz to gigahertz. With further improvements in design and assembly process, a prescaler which could yield better results circuit can be obtained.