Digital design and verification of adaptive noise cancellation module
Vo, Tai (2020)
Lataukset:
Vo, Tai
2020
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Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi:amk-2020112924956
https://urn.fi/URN:NBN:fi:amk-2020112924956
Tiivistelmä
Currently, at Metropolia University Applied of Sciences, digital design and implementation based on DSP studies have mainly focused on how to write efficient codes according to common coding styles rule. However, for its verification process before physical design, verification with an HDL testbench is the only method that is instructed in university. Advanced and high-level verification methods, especially UVM, are still not applied for teaching and studies. Apart from that, when it comes to DSP implementation, adaptive filtering approaches were selected to solve the interesting problem of how to track the statistical variations of signal and eliminate random noise over time in a nonstationary environment with massive datasets and unstructured data types for complex hardware implementation. Therefore, the Thesis work aimed to design and implement an adaptive FIR filtering noise cancellation module based on the LMS algorithm and verify its functional specifications.
In the Thesis work, an adaptive noise cancellation module was developed to be well-prepared for hardware emulation. Module design and verification studied MathWorks work-flow step by step. Matlab reference code was designed and optimized on algorithm level. Simulink model which contains the fixed-point implementation was simulated to be com-pared with Matlab algorithm for periodic discrete-time environment before synthesizing into VHDL. The Register Transfer Level design was verified in cosimulation with Simulink model. Besides, UVM based verification was applied to use System Verilog as verification language to evaluate the fulfillment of functional requirements and guarantee design accuracy with bit-cycle level.
The Thesis presents the design module, which serves the purpose of noise cancellation based on adaptive LMS algorithm. The theory and mathematical model of the design module are explained. RTL reusability was achieved with the use of modular coding style to create instantiated functions. The implementation work was done adhering to Mathwork's digital design flow. Additionally, no errors or bugs were found from the design module under verifications. The module passed all required functionality tests. Hardware deployment and the related challenges, such as IP core generation to be integrated with a register abstraction layer, could be innovated for future development of this Thesis project, since the design module was already modified to be modular and reusable to form a scalable architecture with generic parameter specifications.
In the Thesis work, an adaptive noise cancellation module was developed to be well-prepared for hardware emulation. Module design and verification studied MathWorks work-flow step by step. Matlab reference code was designed and optimized on algorithm level. Simulink model which contains the fixed-point implementation was simulated to be com-pared with Matlab algorithm for periodic discrete-time environment before synthesizing into VHDL. The Register Transfer Level design was verified in cosimulation with Simulink model. Besides, UVM based verification was applied to use System Verilog as verification language to evaluate the fulfillment of functional requirements and guarantee design accuracy with bit-cycle level.
The Thesis presents the design module, which serves the purpose of noise cancellation based on adaptive LMS algorithm. The theory and mathematical model of the design module are explained. RTL reusability was achieved with the use of modular coding style to create instantiated functions. The implementation work was done adhering to Mathwork's digital design flow. Additionally, no errors or bugs were found from the design module under verifications. The module passed all required functionality tests. Hardware deployment and the related challenges, such as IP core generation to be integrated with a register abstraction layer, could be innovated for future development of this Thesis project, since the design module was already modified to be modular and reusable to form a scalable architecture with generic parameter specifications.