Phase Locked Loop (PLL)

Abstract

The main purpose of this project was to design a PLL circuit which can be locked at 1GHZ with four factors of frequency division (10, 20, 40 and 80). Phase Locked Loops (PLLs) are feedback systems that generate phase-locked signals in response to external input sig-nals. PLLs are used to generate an output signal with a programmable frequency., rational multiple of a fixed input frequency. In other words, PLLs are used to lock or track input sig-nals in frequency and phase. When the phase and frequency of the input signals are syn-chronized, the PLL is said to be in the locked condition. The phase difference between the output signal and the reference is a known value when the loop is locked.

To perform the PLL circuit a PCB was designed using PADS, and printed using the milling machine in the university laboratory. The main component of the PLL circuit are Prescaler, Active Loop Filter, Mixer, Power splitter, variable resistor and A voltage-controlled oscillator (VCO). The Prescaler, mixer, power splitter and VCO are surface mount component (SMD).

The goal of this thesis to achieve a locked state of PLL system was not achieved success-fully. After checking and testing the board the results shows that the only thing that not working is the prescaler because the output of it was giving wrong signals to the mixer. Also when changing the division factors they were not affecting in the output.